Silicon-on-insulator (SOI) technology^[1,2] is competitive in comparison to bulk Si technology because of its small isolation area, immunity to latch-up,^[3] and radiation hardening^[4,5] characteristics. The breakdown voltage (BV), a key parameter, is mainly limited by the vertical BV in the SOI device.^[6] Increasing the electrical field in a buried oxide (BOX) is an effective way to improve the vertical BV.^[7] The membrane SOI device etching the Si substrate below the BOX eliminates the vertical BV limit and boosts the BV in the SOI device.^[8,9]

In this paper, a novel structure is proposed to improve the vertical BV limit in an SOI device. In this new structure, one BOX is split into two sections: the source-section BOX and the drain-section BOX. A highly-doped Si layer, referred to as a non-depletion potential-clamped layer (NPCL), is positioned under and close to the two BOX sections. When the new structure is in a blocking state, the blocking voltage is divided into two parts with the assistance of the NPCL. When the device is approaching the BV, the voltage in the NPCL is nearly half of the BV. The voltage sustained by the source-section BOX and the Si region under the source is almost equal to the voltage sustained by the drain-section BOX and the Si region under the drain. Therefore, the vertical BV is doubled. This new structure was verified for a P-channel SOI lateral double-diffused metal-oxide semiconductor (LDMOS) and achieved good results in this study because the vertical BV of a P-channel SOI LDMOS is low as a result of the connection method used for the circuit.^[10]

The novel structure proposed in this paper was verified for an NPCL P-channel SOI LDMOS. The NPCL P-channel SOI LDMOS and the conventional P-channel SOI LDMOS are also referred to as the proposed structure and conventional structure, respectively. In the proposed structure, the NPCL is made up of highly-doped N-type Si. The conventional BOX is split into two sections, with an Si window in the middle. The NPCL is positioned under and close to the two BOX sections. One is the source-section BOX, and the other is the drain-section BOX. A schematic cross-sectional view of the proposed structure is shown in Fig. 1. In this figure, and are the length and concentration of the P drift region, respectively; is the silicon window length; is the thickness of the P drift region; is the thickness of the BOX; and is the thickness of the NPCL. The connection method in the circuit of a P-channel SOI LDMOS can be simplified so that the gate and source are connected to a ground while the drain and substrate are connected to the negative voltage terminal.^[10]

Fig. 1.

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	Fig. 1. Schematic cross section view of NPCL P channel SOI LDMOS.

Reduced surface field (RESURF) technology and field plates are used to improve the lateral BV. Therefore, the vertical BV becomes the limiting factor in the device’s BV. In a conventional P-channel SOI LDMOS, the N body region and P drift region form a diode D1, shown in Fig. 2(a). When a high negative voltage is applied to the drain and substrate,^[10] the voltage drop is mainly sustained by the diode D1. This means that the source-side BOX and the Si region under the source mainly sustain the voltage drop, and this limits the vertical BV.

Fig. 2.

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	Fig. 2. (a) Line around conventional P channel SOI LDMOS, (b) line around NPCL P channel SOI LDMOS, (c) electric field around line in panel (a), and (d) electric field around line in panel (b).

In the proposed structure, when the applied voltage increases, the depletion region expands to the right. Because the NPCL is made up of a highly-doped N type layer, its potential is boosted and remains uniform after the depletion region is reached. As a result of the boosted potential of the NPCL, the drain-section BOX and the Si region under the drain also sustain a voltage drop. When the proposed structure approaches the BV, the voltage sustained by the drain-section BOX and Si region under the drain is nearly equal to the voltage sustained by the source-section BOX and the Si region under the source, and the voltage in the NPCL is almost half of the BV. Therefore, the BV is almost doubled.

To further illustrate the functioning of the proposed structure, a line labelled is drawn around the BOX and Si regions in Figs. 2(a) and 2(b). Figure 2(a) shows a conventional P-channel SOI LDMOS, also referred to as a conventional structure. Figure 2(b) shows the proposed structure. The voltage drop along line is equal to the BV sustained by the device.

The schematic diagrams of the electrical field along line in the conventional structure and the proposed structure are shown in Figs. 2(c) and 2(d), respectively. In Fig. 2(c), the high electrical field along line shows that the source-side BOX and the Si region under the source sustain the voltage, whereas the electrical field along line C’CD is low. The drain-side BOX and the Si region under the drain hardly sustain any voltage. The following formula describes the situation: . In Fig. 2(d), in which the conventional BOX is split into two sections with the NPCL, the high electrical field along line shows that the source-section BOX and the Si region under the source sustain voltage, whereas the high electrical field along line shows that the drain-section BOX and the Si region under the drain also sustain voltage in the proposed structure. The following formula describes this situation: . The proposed structure can sustain a nearly doubled BV. It should be noted that in the above discussion, it is assumed that the electrical fields around the source region and the drain region are equal for brief periods of time. Differences between the N body region, the source region, and the drain region cause the real situation to be slightly different.

The simulation results for the electrical field distribution are shown in Fig. 3. The one-dimensional (1-D) electrical field distribution along line in Figs. 2(a) and 2(b) are plotted in Fig. 3(a). CS denotes the conventional structure. The hollow symbols represent the electrical field along line in the conventional structure at the BV. The points A, in Fig. 3(a) indicate the electrical field at those locations in Fig. 2(a). The peak value of , located at the edge of the N body and P drift regions, is V·cm . The peak value of B on the Si side is V·cm , and the peak value of B on the BOX side is V·cm . This is consistent with the electrical displacement continuity equation for the edge between the Si and the BOX: .^[11] The electrical fields of the peak , C, and D are extremely low and hardly contribute to sustaining the BV. The BV is −202 V in the conventional structure. PS in Fig. 3(a) denotes the proposed structure. The solid symbols represent the electrical field along line in the NPCL P-channel SOI LDMOS at the BV. The electrical field of peak is V·cm . The peak B on the Si side is V·cm , and the peak B on the BOX side is V·cm⁻. The electrical field along line is small. The boosted equipotential of the NPCL makes the drain-section BOX and the Si region under the drain sustain a high electrical field. The electrical field of the peak is V·cm . The peak C on the BOX side is V·cm , and the peak C on the Si side is V·cm . The BV of the proposed structure is −313 V, a 55% improvement over that of the conventional structure. The electrical fields along lines and are not symmetric because of the asymmetry between the source and drain regions in the real device.

Fig. 3.

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	Fig. 3. (a) 1-D electric field distributions along line of conventional P channel SOI LDMOS and NPCL P channel SOI LDMOS, (b) 3-D electric field distributions in conventional P channel SOI LDMOS, and (c) 3-D electric field distributions in NPCL P channel SOI LDMOS. ( m, m, m, m.)

The three-dimensional (3-D) electrical field distributions within the devices can be seen clearly in Figs. 3(b) and 3(c). As Figure 3(b) shows, in the conventional structure, only the source-side BOX and the Si region under the source sustain an electrical field. As Figure 3(c) shows, in the proposed structure, the source-section BOX, the Si region under the source, the drain-section BOX, and the Si region under the drain all sustain an electrical field. This boosts the BV of the device.

The surface electrical field distributions associated with different for the conventional structure and proposed structure are plotted in Fig. 4. The device parameters are identical to those in Fig. 3. The locations of the points I, II, and III are shown in the inset diagram in Fig. 4. was gradually increased to investigate the difference in the surface electrical field between the conventional structure and the proposed structure. When was increased to −100 V, the electrical field at point I was V·cm , the electrical field at point II was V·cm , and the electrical field at point III was nearly 0. was gradually increased until a BV of −202 V was reached. The electrical field at point I was then V·cm , the electrical field at point II was V·cm , and the electrical field at point III was only V·cm . These results indicate that the conventional structure mainly sustains the BV by diode D1 (shown in Fig. 2(b)). In contrast, in the proposed structure, when a of −202 V was applied, the electrical field at point I was V·cm , the electrical field at point II was V·cm , and the electrical field at point III was nearly 0. This situation is similar to that in the conventional structure. However, when was increased steadily, the potential of the NPCL was boosted and contributed to making the drain-section BOX and the Si region under the drain sustain the BV. The proposed structure thus achieved a much higher BV of −313 V. The electrical field at point I was V·cm , the electrical field at point II was V·cm , and the electrical field at point III was nearly V·cm . The enhanced electrical field at point III contributes to the higher BV.

Fig. 4.

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	Fig. 4. Surface electric field of conventional and NPCL P channel SOI LDMOS at various drain voltage.

To illustrate the effect of the Si window length on the BV in the proposed structure, the BVs are plotted as a function of in Fig. 5. The functions of were simulated with different values. The BV achieved by the proposed structure increases with the BOX thickness. For a BOX thickness of 1 m, the BV is −313 V for m, 241V for m, and −167 V for m. The BV decreases as increases. The reason for this is that the permittivity of SiO₂ is much lower than that of Si, and hence the BOX can sustain a higher electric field when is shorter. As increases, the BOX eventually becomes too short to support the electrical field, and the device’s BV decreases.

Fig. 5.

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	Fig. 5. BV versus of NPCL P channel SOI LDMOS.

The on-state characteristics of the conventional structure and the proposed structure are plotted in Fig. 6. In the conventional structure, diode D1 mainly sustains the voltage drop. The decreasing concentration in the P drift region contributes to sustaining a higher BV. However, beyond a certain concentration, breakdown occurs in the device because the maximum electrical field on the source side exceeds the critical electric field. With the help of a field plate, the conventional structure achieves a maximum BV of −202 V at cm . The specific on-resistance ( is 32.3 mm² when is −10 V and is −1 V.

Fig. 6.

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	Fig. 6. as a function of of conventional and NPCL P channel SOI LDMOS ( m, m, m, m).

In the proposed structure, the equipotential layer NPCL is boosted to a high voltage. This facilitates the drain-section BOX and the Si region under the drain sustaining the BV. The proposed structure achieves its maximum BV at a much higher than the conventional structure. The maximum BV is −313 V at cm , and is 10 mm², for the same dimensions and test conditions as for the conventional one. is reduced by 69% in the proposed structure.

The 3-D temperature profiles of the conventional structure and the proposed structure are shown in Fig. 7. In the simulation, the substrate temperature was set to be 300 K, and was set to be −15 V when the devices were under on-state conditions, with a power of 1 mW/ m. Figure 7(b) shows the 3-D temperature profile of the proposed structure. The Si window in the middle of the BOX provides a path to conduct heat away. The temperature profile is low around the Si window, and as a result, the temperature of the entire device is obviously reduced. The T _max of the conventional structure is 334.4 K, whereas the T _max of the proposed structure is only 318.9 K, a reduction of 15.5 K.

Fig. 7.

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	Fig. 7. 3-D temperature distribution in (a) conventional P channel SOI LDMOS, and (b) NPCL P channel SOI LDMOS. ( m, m, m, m).

A novel structure is proposed in this paper for doubling the vertical breakdown voltage of silicon-on-insulator (SOI) devices. The proposed structure was verified for a P-channel NPCL SOI LDMOS by means of simulation. In this new structure, one BOX is split into two sections with the assistance of an NPCL. Under ideal conditions, the new structure can sustain nearly double the vertical BV that a conventional structure can sustain. The simulation results indicate that the BV is improved by 55% and the is reduced by 69% in the proposed structure, in comparison to those in the conventional structure. Furthermore, the window in the middle of the BOXes alleviates the SHE, and T _max is reduced by 15.5 K in the proposed structure. Thus, the new structure is considered a promising technology for use in power SOI devices.